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  - high-performance lsis realized quickly, easily, and at low cost - new asic solution platform issp tm issp1 series issp90 series issp1-std series issp90-std series issp1-hsi series issp90-hsi series nec electronics
2 pamphlet a16092ej8v0pf issp (instant silicon solution platform) is a new asic platform device that helps you create high-performance lsis quickly, easily, and at low cost. as a designer today, you face shorter deadlines for designing lsi products than ever before. issp offers you a risk management solution that enables fast time to market and lower total costs. this solution helps nec electronics satisfy needs that could not be satisfied by conventional asic products and fpga. issp lineup the issp1-std series, nec electronics first-generation issp, is a standard type platform that integrates large-scale sram, and apll and dll circuits. the issp1-std series realizes an operating frequency of up to 250 mhz by employing 5-layer al routing technology using a 0.15 m cmos process. the main applications of this issp include high-speed and high-capacity (broadband) communications or network equipment, computer peripheral equipment, high-performance measuring instruments, and consumer electronic systems. the issp1-hsi series is a high-speed interface core version of the first-generation issp. it supports high-speed interfaces including pci express, gigabit ethernet, and fibre channel, by embedding a high-performance 2.5 gbps serdes (serializer/ deserializer). in addition, ip cores necessary for communications and networks such as spi4.2 (dynamic), 10/100m ethernet mac, 1g ethernet mac, pos phy level 3, and utopia are available as firmware macros, providing the ideal solution for high- speed, high-capacity (broadband) communications, network equipment, and server equipment. the issp90 series, nec electronics' second-generation issp, employs a state-of-the-art 90 nm cmos process. the internal operating frequency of this series is as high as 500 mhz. in addition, the number of user gates is to 6.5 million gates, four times the n umber of the first generation, and the sram capacity has been increased three-fold to 11.5 mb. an embedded serdes core with a data transmission rate of up to 10 gbps is also available, as are the ip cores already provided with the issp1 series. this core can realize a serial interface standard of up to10 gb and a serial ata high-speed interface of 3 gb. a 10 gbps ethernet mac is also available. release period p erformance issp1 series issp1-std 250 mhz (maximum operating frequency) 2002 2003 2004 pd65701 pd65702 pd65703 pd65704 pd65705 pd65706 pd65707 pd65711 pd65712 pd65713 pd65714 issp1-hsi issp90-std issp90-hsi 500 mhz (maximum operating frequency) embedded serdes macro issp90 series logic, memory, and package of larger scale features of issp (1) can realize high-performance system lsis at lower cost than conventional asic/fpga (2) substantially easier design through employment of new architecture (3) many ip cores and high-speed interfaces available (4) high-mix low volume production possible in a short time.
pamphlet a16092ej8v0pf 3 low development risk progress in asic process technology has accelerated in recent years and asics with improved performance and functionality are now widely available to satisfy an ever diverse range of demands. in the meantime, however, new problems have arisen. for e xample, an increase in the number of process steps means a larger number of masks are required. this leads directly to higher development costs. test design, clock design, and signal integrity problems also lengthen the development period, further rais ing the development costs, and the risk to the developer. in the development stage of a new product, an increase in initial costs makes it difficult to estimate payback of investment, placing heavy pressure on the developer's cash flow. in some cases, mass produ ction does not justify the investment. issp can reduce such investment risks by supplying high-performance system lsis at an initial cost equivalent to that of gate arrays. 10 k to 100 k 100 to 1 k life cycle t otal amount fpga area cbic area issp area fpga cbic issp t otal amount t otal development costs 100 to 1 k 10 k to 100 k t otal development costs = labor costs + nre + total amount x unit price t otal number of mass-produced products vs. total costs optimal mass production amount for each device short development period the main causes that extend the development period of conventional asics are problems of test design and mutual interference of signals (signal integrity) resulting from increased miniaturization. fpgas, on the other hand, require a long time to verify circuits if high-speed circuits e xceeding 100 mhz are to be designed. if the cell utiliza- tion rate is high, the design convergence degrades and, in the worst case, the specifications must be reviewed. with issp, the user can concentrate on designing cir- cuits without having to be aware of test design because a test circuit is embedded in advance in the base wafer. in addition, the design period can be shortened due to the employment of a leading-edge process and an embedded clock tree, which increase the performance, and by a new cell structure that counters signal integrity. product development tat (months) product development tat (start of development to mass production) 500 mhz 250 mhz 100 mhz 6 maximum operating frequency issp90 cell-based ic (consumer) cell-based ic (high-end) 18 fpga (low-end) fpga issp1
4 pamphlet a16092ej8v0pf ip core lineup embedded apll/dll ? apll high-speed version: functions: clock skew control function, clock multiplication function, phase shift function, ddr interface input frequency: 25 mhz to 400 mhz output frequency: 25 mhz to 800 mhz medium-speed version: functions: clock skew control function, clock multiplication function input frequency: 12.5 mhz to 400 mhz output frequency: 12.5 mhz to 400 mhz ? ddl functions: ddr interface input frequency: 100 mhz to 175 mhz output frequency: 100 mhz to 175 mhz macro ddr controller 133 mhz, 64 bit 10/100 m ethernet mac 10/100/1000 m mac (triple) ethernet mac tbi (125 mhz, 10 bit) 10 g ethernet mac spi4.2 static dynamic pos phy/utopia level 3 pci-x i/o only serdes up to 2.5 g bps up to 10 g bps pci controller 66 mhz, 32 bit pci express pcs xaui pcs fibre channel pcs issp1 std series hsi pd65701 to pd65704 to series pd65703 pd65707 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? issp90 std hsi series series ? ? ? ? ? ? ? ? ? : supported : to be supported ?: not supported
pamphlet a16092ej8v0pf 5 issp (tool environment) issp (development flow) atprg-e netlist timing constraint lft def not necessary to consider dft customer nec electronics verilog vhdl teraform synplify asic amplify issp design compiler vsim nc- verilog modelsim vcs tiara primetime t ool 1st sign-off standard asic tool new design tool (from nec electronics) interface data 2nd sign-off logic synthesis floor plan gatedrc sta dft (atg) placement routing delay calculation sdf p attern verification timing verification (back annotation) rtl scannet add rtlchecker logic verification clockreplace function fr amework r tl check schematic editor synthesis physical synthesis wa ve editor logic verification sta design rule check fo rm al verification floor plan place & route t ool nec electronics opencad tm issp ? vdraw ? ? wa ve editor v .sim tiara gatedrc, stadrc zero galet, ace-floor plan galet, y-place third party ? te ra fo r m design compiler, synplify asic, amplify asic amplify issp modelsim, nc-verilog, vcs primetime ? conformal-lec, formality amplify issp, soc encounter amplify issp, soc encounter
6 pamphlet a16092ej8v0pf product overview the issp1-std series includes large-scale sram and apll and dll circuits, and employs 5-layer al routing technology using a 0.15 m cmos process, realizing an operation speed of up to 250 mhz. a newly developed complex gate structure is employed for the cells. the lower three routing layers are embedded in advance in the base wafer as complex gate routing, core connection routing, test circuit routing, clock tree routing, and power routing. as a result, the user does not have to consider test design and can concentrate on designing circuits. this results in a substantia lly shorter design period. in addition, the development costs can also be reduced because the user can customize the circuit by us ing just the higher two routing layers. the main applications of the issp1-std series include high-speed, high-capacity (broadband) communications and network systems, computer peripheral equipment, high-performance measuring instruments, and consumer electronic equipment. chip image of issp1-std series apll dll apll apll apll dll dll dll eram e ram e ram e ram e ram e ram e ram e ram e ram e ram e ram e ram clk embedded sram embedded dll embedded apll complex gate test circuits - bscan - multi-scan - bist - testbus embedded clock layer 5 (m5) layer 4 (m4) layer 3 (m3) layer 2 (m2) layer 1 (m1) individual mask shared mask circuit routing for customization power supply, new cell connection routing, test routing, clock domain sequential circuit combinational circuit f/f q b a complex multi-gates q "0" a b mux
pamphlet a16092ej8v0pf 7 master lineup note under development specifications remark the usable package/macro differs depending on the scale of the master. item specification process 0.15 m process, si gate cmos, 2-layer customized routing maximum number of usable gates 1.7 m gates (number of usable issp gates) 3.7 mb (ram capacity) pa c kage tbga 352/420/500/576/768 pins abga 500/756/888 pins fcbga 1155/1521 pins supply voltage i/o block conforms to 3.3 v, 2.5 v, and other high-speed interface standards internal block 1.5 v po w er consumption combinational circuit 0.0267 w/mhz/gate (internal gates) sequential circuit 0.0215 w/mhz/gate (data line cycle/clock line cycle = 4) maximum operating frequency (system clock) 250 mhz (166 mhz) (maximum operating frequency differs depending on the circuit configuration) interface level 3.3 v/2.5 v lvttl 3.3 v pci, pci-x l vds, hstl, sstl, pecl, etc. embedded macro sram 1- or 2-port compiled synchronous apll high-speed type, medium-speed type dll for high-speed sdram interface other macros sram: distributed compiled synchronous sram spi4.2 (dynamic), 10/100/1000 m ethernet mac, 10/100 m ethernet mac, pos phy level 3, utopia, ddr controller, pci controller embedded clock global clock: 2 lines local clock: 2 to 32 lines embedded test-related scan path test, boundary scan, bist, test bus master number of sram size sram apll dll package usable issp high-speed medium-speed gates (bits) 16 k 4 k v ersion v ersion pd65701 214 k 262 k 16 0 3 1 8 tbga: 532/420 pins pd65702 407 k 786 k 48 0 3 1 8 tbga: 420/500/576/680 pins pd65703 941 k 1 m 64 0 3 1 16 tbga: 500/576/680/768 pins pd65704 1 m 3.7 m 216 32 4 0 32 abga: 500/756/888 pins pd65705 1.7 m 2.2 m 128 32 4 0 32 pd65706 1 m 3.7 m 216 32 4 0 32 fcbga: 1155/1521 note pins pd65707 1.7 m 2.2 m 128 32 4 0 32
8 pamphlet a16092ej8v0pf product overview the issp1-hsi series supports high-speed interfaces including pci express, gigabit ethernet (gbe), and fibre channel, by embedding up to 16 high-performance 2.5 gbps serdes (serializer/deserializer) cores, as well as the functions of the issp1-std series. in addition, ip cores necessary for communications and networks such as spi4.2 (dynamic), 10/100 m ethernet mac, 1 g ethernet mac, pos phy level 3, and utopia are available as firmware macros, providing an ideal solution for high-speed, high- capacity (broadband) communications and network equipment and server equipment. the same high-performance 0.15 m cmos process as the existing issp1-std series is used. circuits can also be customized by using just two routing layers. test circ uits and clock tree routing are prepared in advance. therefore, the design and production periods can be dramatically shortened and development costs reduced. issp1-hsi series chip image clk multi-rate high-speed serdes core multi-rate high-speed serdes core (supports gbe, pci express, and fibre channel) tx/rx 8 ch tx/rx 8 ch sram sram inherits issp1-std series platform layer 5 (m5) layer 4 (m4) layer 3 (m3) layer 2 (m2) layer 1 (m1) individual mask shared mask circuit routing for customization power supply new cell connection and routing test routing clock domain sequential circuit combinational circuit f/f q b a complex multi-gates q "0" a b mux
pamphlet a16092ej8v0pf 9 master lineup specifications remark the usable package/macro differs depending on the scale of the master. master number of sram size sram appl dll number of package usable (high-speed serdes issp gates (bits) 16 k 4 k 128 ve rsion) channels pd65711 695 k 729 k 42 0 32 4 8 8 abga: 576/756 pins pd65712 1 m 1 m 56 0 64 4 16 16 abga: 576/756/888 pins pd65713 1.4 m 2 m 112 20 64 4 32 16 abga: 756/888 pins pd65714 1.4 m 2 m 112 20 64 4 32 16 fcbga: 1155 pins item specification process 0.15 m process, si gate cmos, 2 layer customized routing maximum number of usable gates 1.4 m gates (number of usable issp gates) 2 mb (ram capacity) pa c kage abga 576/756/888 pins fcbga 1155 pins supply voltage i/o block conforms to 3.3 v, 2.5 v, and other high-speed interface standards internal block 1.5 v po w er consumption combinational circuit 0.0267 w/mhz/gate (internal gate) sequential circuit 0.0215 w/mhz/gate (data line cycle/clock line cycle = 4) maximum operating frequency (system clock) 250 mhz (166 mhz) (maximum operating frequency differs depending on circuit configuration) interface level 3.3 v/2.5 v lvttl 3.3 v pci, pci-x l vds, hstl, sstl, pecl, etc. embedded high-speed interface macro serdes: supports gbe/pci express/fibre channel embedded macro sram 1- or 2-port compiled synchronous type apll high-speed type dll for high-speed sdram interface other macros spi4.2 (dynamic), 10/100/1000 m ethernet mac, 10/100 m ethernet mac, pos phy level 3, utopia, ddr controller, pci controller embedded clock global clock: 2 lines local clock: 2 to 32 lines embedded test-related scan path test, boundary scan, bist, test bus
10 pamphlet a16092ej8v0pf product overview the issp90 series employs a leading-edge 90 nm cmos process and features an operating frequency of 500 mhz, double that of the issp1 series. in addition, the number of user gates is four times higher (6.5 million gates), and a two-fold sram capacity of 7.0 mb is provided. in addition to the ip cores available in the issp1 series, the issp90 series supplies a serdes embedded core with a data transmission rate of 10 gbps as a high-speed interface indispensable for next-generation applications such as communications, server, and storage. this core can realize a high-speed serial interface standard of 10 gb and high-speed serial ata interface of 3 gb. a 10 gbps ethernet mac is also available. development of issp90 series operating frequency (mhz) 400 500 300 200 100 2002 2003 2004 2005 issp90 series (90 nm) issp1-std 3 types issp1-hsi 4 types issp90-hsi issp90-std issp1-std 4 types development period number of gates: 6.5 m gates max. built-in sram: 7.0 mb max. number of gates: 1.4 m gates max. built-in sram: 2 mb max. embedded serdes core: 2.5 gb max. issp1 series (150 nm) number of gates: 1 m gates max. built-in sram: 1 mb max. number of gates: 3 m gates max. built-in sram: 3 mb max. embedded serdes core: 10 gb max. number of gates: 1.7 m gates max. built-in sram: 3.7 mb max. remark serdes (serializer/deserializer): serial/parallel converter
pamphlet a16092ej8v0pf 11 note depends on the circuit configuration. specifications remark the usable package/macro differs depending on the scale of the master. item specification process 90 nm cmos process, 7 layers (2 customized routing layers) maximum number of usable gates 6.5 m gates (number of usable issp gates) 7.0 mb (ram capacity) pa c kage fcbga 729/1155/1521/1849 pins supply voltage i/o block conforms to 3.3 v, 2.5 v, 1.8 v, and other high-speed interface standards internal block 1.0 v maximum operating frequency (system clock) 500 mhz (333 mhz) (maximum operating frequency differs depending on circuit configuration) interface level 2.5 v lvcmos, lvpecl 2.5 input, 3.3 v lvttl, 2.5 v lvds, hstl class 1/hstl class 3, sstl2 class 1/sstl2 class 2, sstl18. embedded macro sram 2-port compiled synchronous type apll high-speed type dll for high-speed sdram interface (3.3 v master only) other macros spi4.2 (dynamic), 10 g ethernet mac, 10/100/1000 m ethernet mac, 10/100 m ethernet mac, pos phy level 3, utopia, ddr controller, pci controller embedded test-related scan path test, boundary scan, bist, test bus master lineup i/o number of sram size interface master usable issp (bits) gates 3.3 v pd69551 1.74 m 1.11 m pd69552 2.68 m 1.92 m pd69553 3.45 m 2.95 m pd69554 4.00 m 1.77 m pd69555 4.67 m 4.20 m pd69556 5.53 m 2.36 m pd69557 5.40 m 5.68 m pd69558 6.50 m 3.02 m 2.5 v pd69559 5.23 m 7.08 m 3.3 v pd69561 0.87 m 0.77 m pd69562 1.34 m 1.34 m pd69563 1.73 m 2.06 m pd69564 2.00 m 1.24 m pd69565 2.34 m 2.94 m pd69566 2.76 m 1.65 m pd69567 2.70 m 3.97 m pd69568 3.25 m 2.12 m 2.5 v pd69569 2.62 m 4.94 m maximum clock note / pa c kage i/o lineup maximum system (fcbga) clock note sstl2 (2.5 v) 333 mhz/ 729 pins sstl18 (1.8 v) 250 mhz 1155 pins ddr2 (1.8 v) (high density version) 1155 pins hstl18 (1.8 v) 1521 pins pecl (2.5 v) l vds (high speed:3.3 v only) 1155 pins l vds (middle and low 1521 pins speed:2.5 v only) 1849 pins sstl2 (2.5 v) 500 mhz/ 729 pins sstl18 (1.8 v) 333 mhz 1155 pins ddr2 (1.8 v) (high speed version) 1155 pins hstl18 (1.8 v) 1521 pins pecl (2.5 v) l vds (high speed: 3.3 v only) 1155 pins l vds (middle and low 1521 pins speed: 2.5 v only) 1849 pins
12 pamphlet a16092ej8v0pf specifications remark the usable package/macro differs depending on the scale of the master. item specification process 90 nm cmos process, 7 layers (2 customized routing layers) maximum number of usable gates 3 m gates (number of usable issp gates) 3 mb (ram capacity) pa c kage fcbga 729/1155/1521/1849 pins supply voltage i/o block conforms to 3.3 v, 2.5 v, 1.8 v, and other high-speed interface standards internal block 1.0 v maximum operating frequency (system clock) 500 mhz (333 mhz) (maximum operating frequency differs depending on circuit configuration) interface level 2.5 v lvcmos, lvpecl 2.5 input, 3.3 v lvttl, 2.5 v lvds, hstl class 1/hstl class 3, sstl2 class 1/sstl2 class 2, sstl18. high-speed interface embedded macro serdes: supports 10 g serial interface standard (such as 10 g base-r)/3 g serial ata/ xaui/gbe/infiniband/pci express/fibre channel. embedded macro sram 2-port compiled synchronous type apll high-speed type dll for high-speed sdram interface (3.3 v master only) other macros spi4.2 (dynamic), 10 g ethernet mac, 10/100/1000 m ethernet mac, 10/100 m ethernet mac, pos phy level 3, utopia, ddr controller, pci controller embedded test-related scan path test, boundary scan, bist, test bus
pamphlet a16092ej8v0pf 13 issp and opencad are trademarks of nec electronics corporation. te ra fo rm is a registered trademark of tera systems, inc. synplify and amplify are registered trademarks of synplicity, inc. other company names and product names described in this pamphlet are trademarks or registered trademarks of the respective company.
14 pamphlet a16092ej8v0pf the information in this document is current as of september, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the cu sto me r. nec electron ics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. " standard": " special": " specific": these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited.
nec electronics corporation 1753, shimonumabe, nakahara-ku, kawasaki, kanagawa 211-8668, japan tel: 044-435-5111 http://www.necel.com/ [north america] nec electronics america, inc. 2880 scott blvd. santa clara, ca 95050-2554, u.s.a. tel: 408-588-6000 800-366-9782 http://www.necelam.com/ nec electronics shanghai ltd. room 2509-2510, bank of china tower, 200 yincheng road central, pudong new area, shanghai p.r. china p.c:200120 tel: 021-5888-5400 nec electronics taiwan ltd. 7f, no. 363 fu shing north road taipei, taiwan, r. o. c. tel: 02-2719-2377 nec electronics singapore pte. ltd. 238a thomson road, #12-08 novena square, singapore 307684 tel: 6253-8311 [asia & oceania] nec electronics hong kong ltd. 12/f., cityplaza 4, 12 taikoo wan road, hong kong tel: 2886-9318 seoul branch 11f., samik lavied?r bldg., 720-2, yeoksam-dong, kangnam-ku, seoul, 135-080, korea tel: 02-558-3737 for further information, please contact: document no. a16092ej8v0pf00 (8th edition) date published september 2004 n cp(k) c 2002 printed in japan g04.1 [europe] nec electronics (europe) gmbh arcadiastrasse 10 40472 d?sseldorf, germany tel: 0211-65030 http://www.ee.nec.de/ sucursal en espa?a juan esplandiu, 15 28007 madrid, spain tel: 091-504-2787 succursale fran?aise 9, rue paul dautier, b.p. 52 78142 velizy-villacoublay c?dex france tel: 01-3067-5800 filiale italiana via fabio filzi, 25/a 20124 milano, italy tel: 02-667541 branch the netherlands boschdijk 187a 5612 hb eindhoven the netherlands tel: 040-2445845 tyskland filial p.o. box 134 18322 taeby, sweden tel: 08-6380820 united kingdom branch cygnus house, sunrise parkway linford wood, milton keynes mk14 6np, u.k. tel: 01908-691-133


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